3D NAND V9–V12 Process Specifications & Dimensions

Parameter	Samsung V9 (286L)	SK Hynix 321L 4D	Micron G9 (276L)	Kioxia/WD BiCS8 (218L)	YMTC X3 Gen4 (232L)
General Specifications
Stack Architecture	Dual-deck 2×143L	Triple-deck 3×107L	Dual-deck 2×138L	Dual-deck 2×109L	Dual-deck 2×116L
Cell Type	TLC / QLC	TLC / QLC	TLC / QLC	QLC	TLC
Peripheral Circuit	CuA	CuP (4D)	CuA	CuA	Xtacking 3.0
Gate Material	Tungsten (W)	Tungsten (W)	Tungsten (W)	Tungsten (W)	Tungsten (W)
Bit Density TLC (Gb/mm²)	~17.0	~14.75	~21.0	~22.9 (QLC)	~15.0
I/O Speed (Gbps)	3.2	3.6–4.8	3.6	3.2	3.2
Production Status	MP TLC'24 / QLC'26H1	MP H2 2024	MP 2024	MP 2023–24	MP 2023
Process Dimensions
Memory Hole CD (nm)	~120	~115	~120	~120	~120
Memory Hole Pitch (nm)	~158	~155	~158	~158	~156
Bitline Pitch / Eff. Node (nm)	~40 (stuck)	~40 (stuck)	~40 (stuck)	~40 (stuck)	~39
Slit CD / GLS Width (nm)	~60–70	~70–80	~60–70	~60–70	~65–75
Slit Pitch (µm)	~1.2	~1.5	~1.2	~1.2	~1.2
Slit Depth per Deck (µm)	~4.0	~3.0	~3.9	~3.1	~6.35
WL Vertical Pitch (nm) [layer pitch]	~28	~28	~28	~28	~48
WL CD / Conductor Thickness (nm)	~14	~13	~14	~14	~22
WL Lateral Depth ½(MH pitch–MH CD) (nm)	~19	~20	~19	~19	~18
Gate Dielectric ONO (nm)	~22	~22	~22	~22	~22
GLS AR per Deck (Depth ÷ Slit CD)	~62:1	~40:1	~60:1	~48:1	~91:1

V9 Key Characteristics

SK Hynix first to exceed Samsung in raw layer count: 321L (triple-deck) vs Samsung 286L (dual-deck). Triple-deck requires wider slit pitch (~1.5 µm vs ~1.2 µm) to manage wafer stress and block-to-block isolation yield.
All Korean/US manufacturers locked at ~40 nm equivalent lateral node (MH pitch ~155–158 nm). Shrinking below this requires EUV or new etch technology not yet deployed in NAND production.
SK Hynix triple-deck reduces per-deck GLS AR to ~40:1 (vs Samsung ~62:1) — a key yield advantage, even though total channel height is larger.
YMTC 232L outlier: WL vertical pitch ~48 nm (vs ~28 nm for Korean/US peers) — confirmed by TechInsights teardown. Total slit depth ~12.7 µm (2 decks), giving GLS AR per deck ~91:1, explaining YMTC's significant yield and density disadvantage.
Micron G9 achieves highest TLC density (21.0 Gb/mm²) via CuA circuit optimization. Samsung V9 QLC delayed to H1 2026 due to endurance/retention issues at QLC operation.

Parameter	Samsung V10 (4XX-L)	SK Hynix ~430L (est.)	Micron G10 / ~320L (est.)	Kioxia/WD BiCS9 / ~332L (est.)	YMTC ~300L (proj.)
General Specifications
Stack Architecture	Triple-deck (WF-Bonding)	Triple-deck	Triple-deck	Triple-deck	Triple-deck
Cell Type	TLC (1 Tb die)	TLC / QLC	TLC / QLC	TLC / QLC	TLC
Peripheral Circuit	WF-Bonding	CuP + Bonding	CuA + Bonding	CuA	Xtacking 4.0
Gate Material	Molybdenum (Mo)	W → Mo	Tungsten (W)	Tungsten (W)	Tungsten (W)
Bit Density TLC (Gb/mm²)	28.0	~24–26	~22–24	~22–25	~18–20
I/O Speed (GT/s)	5.6	~4.8–5.6	~4.8	~4.8	~3.6
Production Status	DEV ISSCC 2025	DEV	DEV	DEV	PROJ
Process Dimensions (Estimated unless noted)
Memory Hole CD (nm)	~95–100	~100–110	~110–115	~110–115	~115–120
Memory Hole Pitch (nm)	~150–155	~153–158	~155–158	~155–158	~154–158
Bitline Pitch / Eff. Node (nm)	~40 (stuck)	~40 (stuck)	~40 (stuck)	~40 (stuck)	~38–40
Slit CD / GLS Width (nm)	~55–65	~65–75	~60–70	~60–70	~60–70
Slit Pitch (µm)	~1.6–1.8	~1.8–2.0	~1.5–1.8	~1.5–1.8	~1.5
Slit Depth per Deck (µm)	~3.5–3.7	~3.6–4.0	~3.0–3.5	~3.1–3.5	~5.5–6.0
WL Vertical Pitch (nm) [layer pitch]	~25–27	~26–28	~27–29	~27–29	~43–46
WL CD / Conductor Thickness (nm)	~11–12	~12–13	~13–14	~13–14	~20–22
WL Lateral Depth ½(MH pitch–MH CD) (nm)	~27–30	~22–27	~22–24	~22–24	~17–21
Gate Dielectric ONO (nm)	~20–21	~20–22	~21–22	~21–22	~21–22
GLS AR per Deck (Depth ÷ Slit CD)	~55–62:1	~50–58:1	~46–55:1	~47–55:1	~82–95:1

V10 Key Characteristics

Samsung V10 announced at IEEE ISSCC 2025: 4XX-layer, 1 Tb TLC, 28 Gb/mm², 5.6 GT/s — 75% I/O improvement and 65% density gain vs V9.
First use of Molybdenum (Mo) gates (Samsung V10). Mo has lower thin-film resistivity than W, allowing WL CD to shrink to ~11–12 nm without RC delay degradation — critical for 400+L.
Samsung employs WF-Bonding (Wafer Fusion Bonding) for triple-deck integration, skipping the 300-layer tier entirely (286L → 400+L).
Memory hole CD begins to shrink from ~120 nm to ~95–100 nm (Samsung), as improved HAR etch tools support tighter holes. WL lateral depth increases (wider gate wrap-around) — improving cell isolation.
YMTC continues to use thick WL vertical pitch (~43–46 nm vs ~25–27 nm for Samsung), maintaining a large process gap. YMTC GLS AR per deck (~82–95:1) remains significantly worse than Korean/US peers (~50–62:1).
All major manufacturers now converge on triple-deck architecture. Samsung's density lead (28 Gb/mm²) driven by Mo gates + WF-Bonding enabling finer WL vertical pitch.

Parameter	Samsung ~500L (proj.)	SK Hynix ~460L (proj.)	Micron ~380L (proj.)	Kioxia/WD BiCS10 / ~420L (proj.)	YMTC ~360L (proj.)
General Specifications (All Projected / R&D)
Stack Architecture	Quad-deck ~4×125L	Quad-deck ~4×115L	Triple/Quad-deck	Triple/Quad-deck	Triple-deck
Cell Type	TLC / QLC (PLC trial)	TLC / QLC	TLC / QLC	TLC / QLC	TLC
Gate Material	Mo	Mo	W → Mo	W → Mo	W
Bit Density TLC (Gb/mm²)	~35–40	~30–35	~27–30	~28–32	~22–25
I/O Speed (GT/s)	~6.4–8.0	~6.0–7.2	~5.6–6.4	~5.6–6.4	~4.8
Production Status	R&D	R&D	R&D	R&D	PROJ
Process Dimensions (All Projected)
Memory Hole CD (nm)	~80–90	~85–95	~90–100	~90–100	~100–110
Memory Hole Pitch (nm)	~145–152	~148–155	~150–155	~150–155	~153–158
Bitline Pitch / Eff. Node (nm)	~36–38	~37–39	~38–40	~38–40	~40
Slit CD / GLS Width (nm)	~50–60	~55–65	~55–65	~55–65	~60–70
Slit Pitch (µm)	~2.0–2.4	~2.0–2.4	~1.8–2.0	~1.8–2.0	~1.6–1.8
Slit Depth per Deck (µm)	~3.0–3.5	~3.0–3.4	~2.8–3.3	~2.9–3.4	~5.0–5.5
WL Vertical Pitch (nm) [layer pitch]	~22–24	~23–25	~25–27	~25–27	~40–44
WL CD / Conductor Thickness (nm)	~9–11	~10–12	~11–13	~11–13	~18–21
WL Lateral Depth ½(MH pitch–MH CD) (nm)	~30–36	~27–35	~27–32	~27–32	~24–29
Gate Dielectric ONO (nm)	~18–20	~19–21	~19–21	~19–21	~20–22
GLS AR per Deck (Depth ÷ Slit CD)	~56–65:1	~49–58:1	~46–56:1	~48–57:1	~77–88:1

V11 Key Characteristics

500-layer barrier: Quad-deck architecture required for Samsung/SK Hynix. Deck-to-deck bonding overlay error must improve to <2 nm; inter-deck misalignment accumulation across 4 bonds is the primary yield challenge.
WL vertical pitch approaching ~22 nm (Samsung) — near the physical limit where inter-layer SiO₂ (~11 nm) enters quantum tunneling regime, threatening cell data retention and endurance.
Memory hole CD shrinks below 90 nm (Samsung), pushing MH aspect ratio deeper. Advanced HARE (High Aspect Ratio Etch) plasma tools required (next-gen Lam Vantex / TEL Synapse-class).
Mo gate adoption cascade to Micron and Kioxia expected at this generation; W gate RC delay becomes prohibitive above ~400 layers with thin-film conductor constraints.
PLC (5b/cell) technology enters early engineering validation — requires tighter ISPP threshold voltage distribution (<50 mV sigma) and improved ONO charge retention at lower oxide thickness.
YMTC roadmap increasingly constrained by U.S. EAR/BIS export restrictions; domestic Chinese tool substitution (Naura, AMEC) insufficient to replace ASML DUV replenishment and Lam/Applied etch tools at this node.

Parameter	Samsung >530L (proj.)	SK Hynix ~510L (proj.)	Micron ~440L (proj.)	Kioxia/WD ~480L (proj.)	YMTC TBD
General Specifications (Long-term Projections)
Stack Architecture	Quad+ / Novel	Quad-deck	Quad-deck	Quad-deck	TBD
Cell Type	TLC / QLC / PLC (5b)	TLC / QLC / PLC	TLC / QLC	TLC / QLC	TBD
Gate Material	Mo / novel metal	Mo	Mo	Mo	TBD
Bit Density TLC (Gb/mm²)	~45–55	~40–48	~32–38	~35–42	TBD
I/O Speed (GT/s)	~9.6–12.8	~8.0–9.6	~6.4–8.0	~6.4–8.0	TBD
Production Status	PROJ	PROJ	PROJ	PROJ	PROJ
Process Dimensions (Long-term Projections)
Memory Hole CD (nm)	~70–80	~75–85	~80–90	~80–90	TBD
Memory Hole Pitch (nm)	~140–148	~143–150	~145–152	~145–152	TBD
Bitline Pitch / Eff. Node (nm)	<38 (scale break?)	~37–39	~38–40	~38–40	TBD
Slit CD / GLS Width (nm)	~45–55	~48–58	~50–60	~50–60	TBD
Slit Pitch (µm)	~2.4–2.8	~2.2–2.6	~2.0–2.4	~2.0–2.4	TBD
Slit Depth per Deck (µm)	~2.8–3.2	~2.9–3.2	~2.7–3.1	~2.8–3.2	TBD
WL Vertical Pitch (nm) [layer pitch]	~20–22	~21–23	~23–25	~22–24	TBD
WL CD / Conductor Thickness (nm)	~8–10	~9–11	~10–12	~10–12	TBD
WL Lateral Depth ½(MH pitch–MH CD) (nm)	~34–39	~33–38	~28–36	~28–36	TBD
Gate Dielectric ONO (nm)	~16–18	~17–19	~18–20	~18–20	TBD
GLS AR per Deck (Depth ÷ Slit CD)	~57–67:1	~53–62:1	~48–58:1	~50–60:1	TBD

V12 Key Characteristics

Simple layer-count scaling is no longer sufficient. Material (Mo/novel metal gates, 2D gate dielectrics), packaging (Cu-Cu hybrid bonding <1 nm overlay accuracy), and circuit innovation dominate differentiation.
WL vertical pitch approaching ~20 nm (Samsung) — the practical lower limit where inter-layer SiO₂ (~10 nm) is at risk of charge leakage and quantum tunneling, threatening NAND retention without new dielectric materials (e.g., h-BN, Al₂O₃ laminates).
Memory hole AR (per deck) may push toward ~90:1+ for Samsung/SK Hynix — at the limits of current Lam/TEL etch tool plasma density. Next-generation HARE tooling development required.
PLC (5b/cell) likely enters volume production at V12; enables 2.4 Tb die capacity for enterprise storage. Requires on-die LDPC+ ECC hardware and precision ISPP with <40 mV Vt window.
Samsung/SK Hynix may achieve a partial break in the ~40 nm lateral pitch lock at this node, enabled by EUV introduction in NAND patterning or novel SADP schemes, opening the first lateral scaling step since 3D NAND's inception.
YMTC participation at V12 is highly uncertain due to sustained U.S. BIS export controls. Domestic Chinese tool substitution (Naura, AMEC, SMEE) remains inadequate for sub-40 nm HARE etch and advanced ALD at this node.

3D NAND V9–V12: Process Specifications & Dimensions by Manufacturer

V9 Key Characteristics

V10 Key Characteristics

V11 Key Characteristics

V12 Key Characteristics